1. Field of the Invention
The invention relates to a synchronous semiconductor memory device. It particularly relates to a configuration of a data output controlling portion which controls activation/inactivation of an output buffer circuit which in turn outputs data synchronously with a clock signal.
2. Description of the Background Art
A synchronous dynamic random access memory (referred to as "an SDRAM" hereinafter) incorporates external control signals and address signals as well as data synchronously with an externally applied clock signal such as an system clock and also outputs data synchronously with the clock signal. The internal operation manner of the SDRAM is typically determined by states of the external control signals at a rising edge of the clock signal. A combination of states of the external control signals at the rising edge of the clock signal is referred to as "a command". Since the SDRAM takes in the external control signals synchronously with the clock signal and identifies the content of the command, it is not necessary to take into consideration a timing margin for skew of the external control signals or the like, and starting timing of the internal operation can be advanced. Furthermore, since data is input/output synchronously with the clock signal, operating rate of the SDRAM can be determined by the clock signal and an SDRAM operating at high speed can be implemented.
However, typically in data read operation, internal operations are required, starting from applying a read command, internally selecting a memory cell and outputting a valid data. The number of cycles of a clock signal required from the application of the read command to the output of the valid data is referred to as ZCAS latency. The ZCAS latency can be set to an appropriate value of 1, 2, 3, 4 or the like according to an external signal.
Furthermore, in the synchronous dynamic random access memory, a plurality of memory cells are simultaneously selected by one access (i.e., one column selecting operation) and the simultaneously selected memory cells are sequentially accessed synchronously with a clock signal. When reading data, data which is not required by a CPU (central processing unit), which is an external processing unit, may be included in the selected memory cell data. In this case, output data is masked by setting a mask instructing signal DQM which in turn is externally applied at an active state of H level. Typically, data in a cycle in an elapse of the number of clock cycles referred to as DQM latency after mask instructing signal DQM is set to the active state of H level, is masked and is not output. Typically, the DQM latency is set to two.
FIG. 5 schematically shows the entire configuration of a conventional SDRAM. In FIG. 5, the SDRAM includes a memory cell array 1 having a plurality of memory cells arranged in a matrix of rows and columns, an address buffer 2 incorporating address signal bits A0-An externally applied in synchronization with a clock signal CLK and producing an internal address signal, a read circuit 4 activated when reading data for reading data of a memory cell designated by the address signal in memory array 1, and output buffer circuit 6 sequentially outputting the data read from read circuit 4 to a data input/output terminal DQ. In FIG. 5, a circuit portion which selects a row and a column in memory array 1 is not shown in order to simplify the figure.
The SDRAM further includes: a control buffer circuit 8 incorporating externally applied control signals, that is, an external row address strobe signal extZRAS, an external column address strobe signal extZCAS and an external write enable signal extZWE and producing internal control signals; a command decoder 10 identifying states of the internal control signals applied from control buffer circuit 8 to output a triggering signal activating a designated operation mode; an array control circuit 12 outputting a control signal for performing a corresponding designated internal operation in memory array 1 according to an internal operation triggering signal (a row or column selecting operation activating signal) applied from column decoder 10 for application to memory array 1; a read enable circuit 14 producing data read enable signals OEMF and OEMFD in response to activation of a read operation triggering signal R applied from command decoder 10; a DQM buffer 16 incorporating an externally applied data mask instructing signal extDQM synchronously with clock signal CLK and producing an internal mask instructing signal QM; a mask enable circuit 18 delaying internal mask instructing signal QM applied from DQM buffer 16 for a predetermined period and producing a mask enable signal ZQMD; and an output control circuit 20 outputting an output enable signal OEM enabling (i.e., activating) data output operation of output buffer circuit 6 according to data read enable signal OEMFD from read enable circuit 14 and mask enable signal ZQMD from mask enable circuit 18.
Read enable circuit 14 outputs data read enable signal OEMF which is activated for a predetermined period (a clock cycle period represented by burst length) in response to activation of read operation triggering signal R. Furthermore, read enable circuit 14 delays data read enable signal OEMF a predetermined period (a period shorter than the ZCAS latency by one clock cycle) to output read enable signal OEMFD. Mask enable circuit 18 delays mask instructing signal QM by one clock cycle to produce mask enable signal ZQMD.
Output control circuit 20 activates output enable signal OEM when data read enable signal OEMFD is in an active state and mask enable signal ZQMD is in an inactive state. When mask enable signal ZQMD is activated and instructs masking of output data, output control circuit 20 inactivates output enable signal OEM. Now, data read operation of the SDRAM shown in FIG. 5 will be described with reference to the timing chart shown in FIG. 6. FIG. 6 shows a data read operation when the burst length (the number of data successively read but by one read command) is eight, the ZCAS latency is three and the DQM latency is two.
At a certain time prior to time T0, an active command which instructs starting of memory cell selecting operation is applied, and at time T0, a memory cell is in the selected state in memory array 1.
At time T0, a read command which instructs reading data is applied (external control signals extZRAS, extZCAS and extZWE are set to predetermined states at a rising of clock signal CLK) and, according to an internal control signal applied from control buffer circuit 8, command decoder 10 sets read operation triggering signal R to an active state of H level for a predetermined period. In response to the read operation triggering signal R, read enable circuit 14 activates data read enable signal OEMF. The data read enable signal OEMF is kept activated for eight clock cycles (the burst length) following that clock cycle at which the read command is applied. Furthermore, read enable circuit 14 delays data read enable signal OEMF two clock cycles to activate read enable signal OEMFD. Thus, data read enable signal OEMFD is kept activated for eight clock cycles at an elapse of two clock cycles according to the read command applied at time T0 (i.e., from the cycle starting at time T2). In response to the activation of data read enable signal OEMF, read circuit 4 is activated and data of the memory cells selected in memory array 1 is read out. Furthermore, the read command designates column selecting operation and also selects memory cells from the memory cells which in turn have been selected in memory array 1 according to the active command.
In a clock cycle starting at time T2, data read enable signal OEMFD is activated. At that time, mask enable signal ZQMD is still in an inactive state of H level and output control circuit 20 activates data output enable signal OEM. Thus, output buffer circuit 6 is enabled and outputs data applied from read circuit 4 synchronously with the clock signal.
At the rising edge of clock signal CLK at time T3, external mask instructing signal extDQM is set to an active state of H level. In response to the activated mask instructing signal extDQM, mask instructing signal QM which is set to H level for a predetermined period is output from DQM buffer 16. The mask instructing signal QM is delayed by mask enable circuit 18 by two clock cycles. Thus, at time T4, mask enable signal ZQMD is still at H level of an inactive state and, in this cycle also, output enable signal OEM is in an active state and output buffer circuit 6 outputs data.
At time T5, mask enable signal ZQMD from mask enable circuit 18 is set to an active state of L level and accordingly output control circuit 20 inactivates output enable signal OEM. Accordingly, output buffer circuit 6 is inactivated and data output operation is stopped. Thus, data is not output in a cycle starting at time T5.
Since external mask instructing signal extDQM is activated for only one clock cycle period, mask enable signal ZQMD is again inactivated in a clock cycle starting at time T6 and accordingly data output enable signal OEM is activated. Thus, output buffer circuit 6 outputs data applied from read circuit 4 to data output terminal DQ.
In the clock cycle starting at time T8, read enable signal OEMF is set to L level of an inactive state (data read enable signal OEMF is reset according to a reset signal RESET which is output from a burst length counter described later) and read circuit 4 is thus inactivated. There is a delay in data transfer from read circuit 4 to output buffer circuit 6. Since data read enable signal OEMFD is in an active state, output enable signal OEM from output control circuit 20 is maintained at an active state and output buffer circuit 6 sequentially outputs data applied from read circuit 4 in synchronization with clock signal CLK. In a clock cycle starting at time T10, read enable signal OEMFD is inactivated, output enable signal OEM is accordingly inactivated, and output buffer circuit 6 is inactivated, and is set to an output high impedance state.
As described above, data can be sequentially output synchronously with clock signal CLK and data can be read out at high speed.
Furthermore, by employing mask instructing signal extDQM, output of unnecessary data can be inhibited.
The number of clock cycles between time T0 at which a read command is supplied and time T3 at which valid data is first output at data input/output terminal DQ is referred to as ZCAS latency, and an interval from time T3 at which external mask instruction signal extDQM is activated to time T5 at which output data is masked is referred to as DQM latency.
FIG. 7 schematically shows configurations of read enable circuit 14, mask enable circuit 18 and output control circuit 20 shown in FIG. 5. In FIG. 7, read enable circuit 14 includes an OEMF generating circuit 14a responsive to read operation triggering signal R for generating read enable signal OEMF activated for a predetermined period and an (N-1)-clock shift circuit 14b which delays read enable signal OEMF applied from OEMF generating circuit 14a by (N-1) clock cycles, wherein N represents the ZCAS latency.
Mask enable circuit 18 includes an inverter 18a which receives mask instructing signal QM and a one-clock shift circuit 18b which delays an output signal of inverter 18a by one clock cycle.
Output control circuit 20 includes two-input AND circuit 20a which receives a delayed read enable signal OEMFD from (N-1)-clock shift circuit 14b and mask enable signal ZQMD from one-clock shift circuit 18b and outputs output enable signal OEM. (N-1)-clock shift circuit 14b and one-clock shift circuit 18b delay input signals as required by shifting the signals applied to their input portions in synchronism with clock signal CLK.
As shown in FIG. 7, read enable circuit 14 and mask enable circuit 18 are individually provided with shift circuits 14b and 18b, respectively. Therefore, layout area of data output operation controlling portion is undesirably increased.
FIG. 8 shows timing relationship between data output enable signal OEM and clock signal CLK. When output enable signal OEM rises in response to activation of read enable signal OEMFD, the rising of output enable signal OEM is determined by responsibility of (N-1)-clock shift circuit 14b included in read enable circuit 14 to clock signal CLK, and output enable signal OEM is set to an active state of H level after an elapse of time ta0 since a rising of clock signal CLK. Furthermore, when output enable signal OEM is inactivated in response to inactivation of read enable signal OEMFD, output enable signal OEM is set to an inactive state of L level after an elapse of time tb0 since a rising of clock signal CLK, similarly according to operation characteristic of (N-1)-clock shift circuit 14b of read enable circuit 14.
On the other hand, when output enable signal OEM is changed according to mask instructing signal QM, output enable signal OEM is activated/inactivated via mask enable circuit 18. That is, when mask enable signal ZQMD is set to L level, output enable signal OEM is set to L level of an inactive state. When mask enable signal ZQMD is set to an inactive state of H level, output enable signal OEM returns to an active state of H level. When masking, according to operation characteristic of one-clock shift circuit 18b, output enable signal OEM is inactivated after an elapse of time tb1 since a rising of clock signal CLK. Furthermore, during a mask, output enable signal OEM is set to an active state of H level after an elapse of time ta1 since a rising of clock signal CLK to H level.
In FIG. 8, responsibility of output enable signal OEM to mask enable signal ZQMD is shown being slower than that of output enable signal OEM to read enable signal OEMFD, which is merely illustrative. Thus, if responsibilities of clock shift circuits 14b and 18b to the clock signal are different from each other, timing of activation/inactivation of output enable signal OEM is different with respect to a changing point of clock signal CLK, such a change of timing of defining of output enable signal OEM should be taken into consideration in outputting data, which means that data cannot be output at high speed. Even if clock shift circuits 14b and 18b have the same responsibility with respect to clock signal CLK, if the distance between output control circuit 30 and read enable circuit 14 is different from that between output control circuit 20 and mask enable circuit 18, the interconnection line lengths are different, propagation delays of signals OEMFD and ZQMD are accordingly different from each other and timing of change of output enable signal OEM is similarly different with respect to a changing point of clock signal CLK.
Thus, since enabling (activation)/disabling (inactivation) of the output buffer circuit is different with respect to clock signal CLK, valid data may be partially masked or data to be masked may not be entirely masked so that accurate data output may not be achieved.